1. Engage in logic design verification of MCU and communication / navigation baseband based on top process nodes (28nm, 14 / 12NM), and advanced peripherals (DDR, Gigabit Ethernet, etc.). Extract test targets and write incentives;
2. Responsible for developing module level and system level verification environment, verification script tools, and maintaining verification process;
3. Work closely with design engineers to understand module and chip design specifications;
4. Be able to develop on the test platform, direct test case and randomized test case design and function coverage generation based on high-level hardware language such as SystemVerilog are preferred;
5. Be able to cooperate with design and firmware engineers to verify and debug FPGA platform, and apply advanced verification methods to project verification.
1. Proficient in Verilog / SystemVerilog RTL verification, with more than two years of practical engineering design experience;
2. Familiar with IP integration process;
3. Familiar with FPGA debugging;
4. Familiar with Perl or Python scripting language is preferred.